Test system that performs simultaneous tests of multiple test units

ABSTRACT

A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. Non-provisional application claims priority under 35 USC §119to Korean Patent Application No. 10-2014-0107246, filed on Aug. 18,2014, in the Korean Intellectual Property Office (KIPO), the disclosureof which is incorporated by reference in its entirety herein.

BACKGROUND

1. Technical Field

Example embodiments relate generally to test systems, and moreparticularly to test systems that can test a plurality of test units.

2. Discussion of the Related Art

As manufacturing processes of semiconductors have been developed, designrules to design semiconductor may increase. The design rules areverified through test units having various layout patterns on a siliconwafer. The number of pads which transfer signals between test units andoutside of a test system including the test units is relatively smallcompared to the number of the test units.

SUMMARY

According to example embodiments, a test system includes a row decoder,a column decoder, a row test controller, and a test circuit. The rowdecoder activates one of first through M-th row signals, where M is apositive integer 1, 2, 3 . . . , based on a plurality of row inputsignals. The column decoder activates one of first through N-th columnsignals, where N is a positive integer, based on a plurality of columninput signals. The row test controller outputs first through N-th columnoutput signals, which are activated, when a row test enable signal isactivated. The row test controller outputs the first through N-th columnsignals as the first through N-th column output signals respectivelywhen the row test enable signal is deactivated. The test circuitincludes first through M-th row test blocks, each of which includesfirst through N-th test units. The first through M-th row test blockscorrespond to the first through M-th row signals, respectively. The testcircuit simultaneously performs a short test of the first through N-thtest units included in a row test block, which corresponds to activatedrow signal among the first through M-th row signals, based on first andsecond test signals and the first through N-th column output signalswhen the row test enable signal is activated.

In an example embodiment, the test circuit may perform short test of atest unit, which corresponds to the activated row signal among the firstthrough M-th row signals and activated column output signal among thefirst through N-th column output signals, based on the first and secondtest signals when the row test enable signal is deactivated.

In an example embodiment, a result of the short test of the firstthrough N-th test units may represent success when an input current isapplied as the first test signal and the input current is not measuredas the second test signal, and the result of the short test of the firstthrough N-th test units may represent failure when the input current isapplied as the first test signal and the input current is measured asthe second test signal.

In an example embodiment, if the result of the short test of the firstthrough N-th test units represents failure, the row test enable signalmay be deactivated and the test circuit may separately perform the shorttest of each of the first through N-th test units included in the rowtest block, which corresponds to the activated row signal among thefirst through M-th row signals, again.

In an example embodiment, the K-th row test block, where K is a positiveinteger equal to or less than M, may include a row switch and firstthrough N-th column switches. The first test signal may be applied to afirst terminal of the row switch, a second terminal of the row switchmay be connected to a first node, and the first and second terminals ofthe row switch may be connected or disconnected based on the K-th rowsignal. The second test signal may be output from a second node, firstterminals of the first through N-th column switches may be connected tothe second node, second terminals of the first through N-th columnswitches may be connected to the first node through the first throughN-th test units respectively, and the first and second terminals of eachof the first through N-th column switches may be connected ordisconnected based on each of the first through N-th column outputsignals.

In an example embodiment, the row switch and the first through N-thcolumn switches may include a pass transistor, respectively.

In an example embodiment, the K-th row test block, where K is a positiveinteger equal to or less than M, may include a row switch and firstthrough 2N-th column switches. The first test signal may be applied to afirst terminal of the row switch, a second terminal of the row switchmay be connected to a first node, and the first and second terminals ofthe row switch may be connected or disconnected based on the K-th rowsignal. The second test signal may be output from a second node, firstterminals of the first through N-th column switches may be connected tothe second node, second terminals of the first through N-th columnswitches may be connected to first terminals of the N+1-th through 2N-thcolumn switches through the first through N-th test units respectively,second terminals of the N+1-th through 2N-th column switches may beconnected to the first node, the first and second terminals of each ofthe first through N-th column switches may be connected or disconnectedbased on each of the first through N-th column output signals, and thefirst and second terminals of each of the N+1-th through 2N-th columnswitches may be connected or disconnected based on each of the firstthrough N-th column output signals.

In an example embodiment, the row switch and the first through 2N-thcolumn switches may include a pass transistor, respectively.

In an example embodiment, the test system may be embodied on a siliconsubstrate. The test system may include a plurality of row input signalmetals, first and second test signal metals, row test enable signalmetal, and a plurality of column input signal metals on the siliconsubstrate.

In an example embodiment, an insulation layer may be on the siliconsubstrate. The insulation layer may include a plurality of row inputsignal pads, first and second test signal pads, a row test enable signalpad, and a plurality of column input signal pads on the insulationlayer. The insulation layer may include first connection metalsconnecting the row input signal pads and the row input signal metalsrespectively, a second connection metal connecting the first test signalpad and the first test signal metal, a third connection metal connectingthe second test signal pad and the second test signal metal, a fourthconnection metal connecting the row test enable signal pad and the rowtest enable signal metal, and fifth connection metals connecting thecolumn input signal pads and the column input signal metals. The rowinput signals may be provided to the row decoder through the row inputsignal pads, the first connection metals, and the row input signalmetals, respectively. The column input signals may be provided to thecolumn decoder through the column input signal pads, the fifthconnection metals, and the column input signal metals, respectively. Therow test enable signal may be provided to the row test controllerthrough the row test enable signal pad, the fourth connection metal, andthe row test enable signal metal. The first test signal generated by anexternal current source may be provided to the test circuit through thefirst test signal pad, the second connection metal, and the first testsignal metal. The second test signal generated by the test circuit maybe provided to an external current measurement circuit through thesecond test signal metal, the third connection metal, and the secondtest signal pad.

In an example embodiment, the row test controller may include firstthrough N-th OR gates. Each of the first through N-th OR gates maygenerate each of the first through N-th column output signals byperforming logic OR operation on the row test enable signal and each ofthe first through N-th column signals.

According to example embodiments, a test system includes a row decoder,a column decoder, and a test circuit. The row decoder activates one offirst through M-th row signals, where M is a positive integer based on aplurality of row input signals. The column decoder activates one ofsignals, which includes a row test enable signal and first through N-thcolumn signals, where N is a positive number, based on a plurality ofcolumn input signals. The test circuit includes first through M-th rowtest blocks, each of which includes first through N-th test units. Thefirst through M-th row test blocks correspond to the first through M-throw signals, respectively. The test circuit simultaneously performs anopen test of the first through N-th test units included in a row testblock, which corresponds to activated row signal among the first throughM-th row signals, based on first and second test signals and the firstthrough N-th column signals when the row test enable signal isactivated.

In an example embodiment, the test circuit may perform an open test of atest unit, which corresponds to the activated row signal among the firstthrough M-th row signals and activated column signal among the firstthrough N-th column signals, based on the first and second test signalswhen the row test enable signal is deactivated.

In an example embodiment, a result of the open test of the first throughN-th test units may represent success when an input current is appliedas the first test signal and the input current is measured as the secondtest signal. The result of the open test of the first through N-th testunits may represent failure when the input current is applied as thefirst test signal and the input current is not measured as the secondtest signal.

In an example embodiment, if the result of the open test of the firstthrough N-th test units represents failure, the row test enable signalmay be deactivated and the test circuit may separately perform the opentest of each of the first through N-th test units included in the rowtest block, which corresponds to the activated row signal among thefirst through M-th row signals, again.

In an example embodiment, the K-th row test block, where K is a positiveinteger equal to or less than M, may include first through third rowswitches and first through 2N-th column switches. The first test signalmay be applied to a first terminal of the first row switch, a secondterminal of the first row switch may be connected to a first node, thefirst and second terminals of the first row switch may be connected ordisconnected based on the K-th row signal. A first terminal of theL+1-th test unit, where L is a positive integer less than N, may beconnected to a second terminal of the L-th test unit. A first terminalof the second row switch may be connected to the first node, a secondterminal of the second row switch may be connected to a first terminalof the first test unit, and the first and second terminals of the secondrow switch may be connected or disconnected based on the row test enablesignal. A first terminal of the third row switch may be connected to asecond terminal of the N-th test unit, a second terminal of the thirdrow switch may be connected to a second node, the second test signal maybe output from the second node, and the first and second terminals ofthe third row switch may be connected or disconnected based on the rowtest enable signal. First terminals of the first through N-th columnswitches may be connected to the second node, second terminals of thefirst through N-th column switches may be connected to the secondterminals of the first through N-th test units respectively, and thefirst and second terminals of each of the first through N-th columnswitches may be connected or disconnected based on each of the firstthrough N-th column signal. First terminals of the N+1-th through 2N-thcolumn switches may be connected to the first node, second terminals ofthe N+1-th through 2N-th column switches are connected to the firstterminals of the first through N-th test units respectively, and thefirst and second terminals of each of the N+1-th through 2N-th columnswitches are connected or disconnected based on each of the firstthrough N-th column signal.

In an example embodiment, the first through third row switches and thefirst through 2N-th column switches may include a pass transistor,respectively.

In an example embodiment, the test system may be embodied on a siliconsubstrate. The test system may include a plurality of row input signalmetals, first and second test signal metals, and a plurality of columninput signal metals on the silicon substrate.

In an example embodiment, an insulation layer may be on the siliconsubstrate. The insulation layer may include a plurality of row inputsignal pads, first and second test signal pads, and a plurality ofcolumn input signal pads on a surface of the insulation layer. Theinsulation layer may include first connection metals connecting the rowinput signal pads and the row input signal metals respectively, a secondconnection metal connecting the first test signal pad and the first testsignal metal, a third connection metal connecting the second test signalpad and the second test signal metal, and fourth connection metalsconnecting the column input signal pads and the column input signalmetals. The row input signals may be provided to the row decoder throughthe row input signal pads, the first connection metals, and the rowinput signal metals, respectively. The column input signals may beprovided to the column decoder through the column input signal pads, thefourth connection metals, and the column input signal metals,respectively. The first test signal generated by an external currentsource may be provided to the test circuit through the first test signalpad, the second connection metal, and the first test signal metal. Thesecond test signal generated by the test circuit may be provided to anexternal current measurement circuit through the second test signalmetal, the third connection metal, and the second test signal pad.

In an example embodiment, a test system may include a test circuitincluding a plurality of test blocks, a respective one of which includesa plurality of test units. The test circuit is configured tosimultaneously perform a test on a plurality of test units in one of theplurality of test blocks and, upon failure of all the test units to passthe test that is performed simultaneously, to separately perform thetest on a respective one of the plurality of test units in the one ofthe plurality of test blocks.

In example embodiments, the test is a short test that represents failurewhen a current is applied to a first node of the test unit and thecurrent is measured at a second node of the test unit.

In example embodiments, the test is an open test that represents failurewhen a current is applied to a first node of the test unit and thecurrent is not measured at a second node of the test unit.

In example embodiments, the test circuit is embodied on a single siliconsubstrate. In some embodiments, the plurality of test units comprise aplurality of layout patterns in the single silicon substrate, at leasttwo of which include different design rules.

As described above, the test system according to example embodimentschanges 2D addressable test site, which tests a plurality of test unitsselected by row signals and column signals for using relatively smallpads efficiently, such that short tests or open tests of the test unitsincluded in a row may be performed simultaneously based on a row testenable signal, and test time of the test units may be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments of the inventive concepts will be more clearlyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings.

FIG. 1 is a block diagram illustrating a test system according to anexample embodiment.

FIG. 2 is a block diagram illustrating the first row test block includedin the test system of FIG. 1.

FIG. 3 is a circuit diagram illustrating an example embodiment of thefirst circuit included in the first row test block of FIG. 2.

FIGS. 4 through 7 are diagrams illustrating example embodiments oflayouts of the first, second, N−1-th, and N-th test units included inthe first row test block of FIG. 2.

FIG. 8 is a block diagram illustrating the first row test block includedin the test system of FIG. 1.

FIG. 9 is a block diagram illustrating a row test controller included inthe test system of FIG. 1.

FIG. 10 is a sectional view of a test system according to an exampleembodiment.

FIG. 11 is a block diagram illustrating a test system according toanother example embodiment.

FIG. 12 is a block diagram illustrating the first row test blockincluded in the test system of FIG. 11.

FIGS. 13 through 15 are diagrams illustrating example embodiments oflayouts of the first, N−1-th, and N-th test units included in the firstrow test block of FIG. 12.

FIG. 16 is a sectional view of an example embodiment implementing thetest system of FIG. 11.

FIG. 17 is a flowchart of operations of a test system according toexample embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will be described more fully hereinafterwith reference to the accompanying drawings, in which some exampleembodiments are shown. The present inventive concepts may, however, beembodied in many different forms and should not be construed as limitedto the example embodiments set forth herein. Rather, these exampleembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present inventiveconcepts to those skilled in the art. In the drawings, the sizes andrelative sizes of layers and regions may be exaggerated for clarity.Like numerals refer to like elements throughout.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are used to distinguish oneelement from another. Thus, a first element discussed below could betermed a second element without departing from the teachings of thepresent inventive concepts. As used herein, the term “and/or” includesany and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “connected” to another element, it can be directlyconnected or connected to the other element or intervening elements maybe present. In contrast, when an element is referred to as being“directly connected” or “directly connected” to another element, thereare no intervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between,” “adjacent” versus “directlyadjacent,” etc.).

It also will be understood that, as used herein, the terms “row” and“column” indicate two non-parallel directions that may be orthogonal toone another. However, the terms row and column do not indicate aparticular horizontal or vertical orientation.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of thepresent inventive concepts. As used herein, the singular forms “a,” “an”and “the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will be further understood thatthe terms “comprises” and/or “comprising,” when used in thisspecification, specify the presence of stated features, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, steps, operations,elements, components, and/or groups thereof.

It should also be noted that in some alternative implementations, thefunctions/acts noted in the blocks may occur out of the order noted inthe flowcharts. For example, two blocks shown in succession may in factbe executed substantially concurrently or the blocks may sometimes beexecuted in the reverse order, depending upon the functionality/actsinvolved.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which these inventive concepts belong.It will be further understood that terms, such as those defined incommonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

FIG. 1 is a block diagram illustrating a test system according to anexample embodiment.

Referring to FIG. 1, a test system 100 includes a row decoder RD 150, acolumn decoder CD 170, a row test controller CLEC 160, and a testcircuit 110. The test circuit 110 includes first through M-th row testblocks RTC1 (120), RTC2 through RTCM−1, RTCM, each of which includesfirst through N-th test units DUT1, DUT2 through DUTN−1, DUTN.

In some embodiments, the test units are two-terminal layout patterns ina silicon semiconductor wafer, wherein the configuration and/ordimensions of the layout pattern may vary depending upon the designrules that are used. A given test unit may be duplicated in the testcircuit, to allow statistical testing. Moreover, a variety differenttest units may be provided, which may have a similar pattern butdifferent design rules, which may have different patterns and the samedesign rules and/or may have different patterns and different designrules. In order to verify the design rules, large numbers of test unitsmay be provided. In the Figures, the test units may be representedschematically by a resistor because, in some embodiments, the test unitsmay be represented by line patterns having a resistance. However, morecomplex test units also may be provided.

The row decoder 150 activates one of first through M-th row signals RS1,RS2 through RSM−1, RSM based on a plurality of row input signals RIS1through RISP. M is a positive integer, i.e., 1, 2, 3, 4 . . . . Thecolumn decoder 170 activates one of first through N-th column signalsCS1, CS2 through CSN−1, CSN based on a plurality of column input signalsCIS1 through CISQ. N is a positive integer. The row test controller 160outputs first through N-th column output signals COS1, COS2 throughCOSN−1, COSN, which are activated, when a row test enable signal RTS isactivated. The row test controller 160 outputs the first through N-thcolumn signals CS1, CS2 through CSN−1, CSN as the first through N-thcolumn output signals COS1, COS2 through COSN−1, COSN respectively whenthe row test enable signal RTS is deactivated.

The first through M-th row test blocks RTC1 (120), RTC2 through RTCM−1,RTCM correspond to the first through M-th row signals RS1, RS2 throughRSM−1, RSM, respectively. The test circuit 110 simultaneously performsshort test of the first through N-th test units included in a row testblock, which corresponds to activated row signal among the first throughM-th row signals RS1, RS2 through RSM−1, RSM, based on first and secondtest signals TS1, TS2 and the first through N-th column output signalsCOS1, COS2 through COSN−1, COSN when the row test enable signal RTS isactivated.

The test circuit 110 may perform short test of a test unit, whichcorresponds to the activated row signal among the first through M-th rowsignals RS1, RS2 through RSM−1, RSM and activated column output signalamong the first through N-th column output signals COS1, COS2 throughCOSN−1, COSN, based on the first and second test signals TS1, TS2 whenthe row test enable signal RTS is deactivated.

FIG. 17 is a flowchart illustrating operation of a test circuit, such asthe test circuit 110, according to various embodiments. Referring toFIG. 17, at Block 1710, a test is simultaneously performed on all testunits in one test block, such as a test block 120 of FIG. 1. If all testunits in the one test block pass the test, then a determination is madeat Block 1740 as to whether additional test blocks have not yet beentested. If so, they are tested by returning operations to Block 1710.Alternatively, if all of the test units do not pass the test at Block1720, then at Block 1730, the test is separately performed on theindividual test units in the one test block. Accordingly, in FIG. 17,the test circuit 110 is configured to simultaneously perform a test on aplurality of test units DUT in one of the plurality of test blocks 120and, upon failure of all the test units DUT to pass the test that isperformed simultaneously, to separately perform the test on a respectiveone of the plurality of test units DUT in the one of the plurality oftest blocks 120. The plurality of test units may comprise a plurality oflayout patterns in the single silicon substrate, at least two of whichinclude different design rules.

A procedure of simultaneous short test of the first through N-th testunits DUT1, DUT2 through DUTN−1, DUTN and a procedure of separate shorttest of the first through N-th test units DUT1, DUT2 through DUTN−1,DUTN will be described with the references to FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the first row test block includedin the test system of FIG. 1.

Referring to FIG. 2, the first row test block 120 a may include a rowswitch SRa and first through N-th column switches S1 a S2 a throughSN−1a, SNa. The second through M-th row test block RTC2, RTCM−1, RTCMincluded in the test system 100 of FIG. 1 may have the same or similarstructure with the first row test block 120 a.

The first test signal TS1 may be applied to a first terminal of the rowswitch SRa. A second terminal of the row switch SRa may be connected toa first node 122 a. The first and second terminals of the row switch SRamay be connected or disconnected based on the first row signal RS1. Thesecond test signal TS2 may be output from a second node 121 a. Firstterminals of the first through N-th column switches S1 a, S2 a throughSN−1a, SNa may be connected to the second node 121 a. Second terminalsof the first through N-th column switches S1 a, S2 a through SN−1a, SNamay be connected to the first node 122 a through the first through N-thtest units DUT1 a, DUT2 a through DUTN−1a, DUTNa respectively. The firstand second terminals of each of the first through N-th column switchesS1 a, S2 a through SN−1a, SNa may be connected or disconnected based oneach of the first through N-th column output signals COS1, COS2 throughCOSN−1, COSN.

The first and second terminals of the row switch SRa may be connected(shorted) when the first row signal RS1 is activated. The first andsecond terminals of the row switches SRa may be disconnected (opened)when the first row signal RS1 is deactivated. The first and secondterminals of each of the first through N-th column switches S1 a, S2 athrough SN−1a, SNa may be connected when each of the first through N-thcolumn output signals COS1, COS2 through COSN−1, COSN is activated. Thefirst and second terminals of each of the first through N-th columnswitches S1 a, S2 a through SN−1a, SNa may be disconnected when each ofthe first through N-th column output signals COS1, COS2 through COSN−1,COSN is deactivated.

In an example embodiment, the first through N-th test units DUT1 a, DUT2a through DUTN−1a, DUTNa may have the same circuit structure, but mayhave different layout patterns. Example embodiments of layouts of thefirst through N-th test units DUT1 a, DUT2 a through DUTN−1a, DUTNa willbe described with the references to FIGS. 4 through 7.

Two terminals of the row switch SRa are connected (shorted) and twoterminals of each of the first through N-th column switches SR1 a, SR2 athrough SRN−1a, SRNa are connected when the first row signal RS1 isactivated and activated row test enable signal RTS is applied to the rowtest controller 160. If the input current is applied as the first testsignal TS1 and the input current is not measured as the second testsignal TS2, two terminals of each of the first through N-th test unitsDUT1 a, DUT2 a through DUTN−1a, DUTNa are disconnected, and the resultof the short test of the first through N-th test units DUT1 a, DUT2 athrough DUTN−1a, DUTNa represents success. In other words, the fact thatall of the first through N-th test units DUT1 a, DUT2 a through DUTN−1a,DUTNa are opened may be indicated by one test.

If the input current is applied as the first test signal TS1 and theinput current is measured as the second test signal TS2, two terminalsof at least one of the first through N-th test units DUT1 a, DUT2 athrough DUTN−1a, DUTNa are connected, and the result of the short testof the first through N-th test units DUT1 a, DUT2 a through DUTN−1a,DUTNa represents failure. In other words, the fact that not all of thefirst through N-th test units DUT1 a, DUT2 a through DUTN−1a, DUTNa areopened may be indicated. In this case, the test circuit 110 separatelyperforms short test of each of the first through N-th test units DUT1 a,DUT2 a through DUTN−1a, DUTNa again by deactivating the row test enablesignal RTS, activating the first through N-th column output signalsCOS1, COS2 through COSN−1, COSN sequentially.

Two terminals of the row switch SRa are connected, two terminals of thefirst column switch S1 a are connected, and two terminals of each ofother column switches S2 a through SN−1a, SNa are disconnected when thefirst row signal RS1 is activated, the row test enable signal RTS isdeactivated, and the first column output signal COS1 is activated. Ifthe input current is applied as the first test signal TS1 and the inputcurrent is not measured as the second test signal TS2, two terminals ofthe first test unit DUT1 a are disconnected. If the input current isapplied as the first test signal TS1 and the input current is measuredas the second test signal TS2, two terminals of the first test unit DUT1a are connected.

Two terminals of the row switch SRa are connected, two terminals of thesecond column switch S2 a are connected, and two terminals of each ofother column switches (S1 a, SN−1a, and SNa) are disconnected when thefirst row signal RS1 is activated, the row test enable signal RTS isdeactivated, and the second column output signal COS2 is activated. Ifthe input current is applied as the first test signal TS1 and the inputcurrent is not measured as the second test signal TS2, two terminals ofthe second test unit DUT2 a are disconnected. If the input current isapplied as the first test signal TS1 and the input current is measuredas the second test signal TS2, two terminals of the second test unitDUT2 a are connected.

Two terminals of the row switch SRa are connected, two terminals of theN−1-th column switch SN−1a are connected, and two terminals of each ofother column switches (S1 a, S2 a, and SNa) are disconnected when thefirst row signal RS1 is activated, the row test enable signal RTS isdeactivated, and the N−1-th column output signal COSN−1 is activated. Ifthe input current is applied as the first test signal TS1 and the inputcurrent is not measured as the second test signal TS2, two terminals ofthe N−1-th test unit DUTN−1a are disconnected. If the input current isapplied as the first test signal TS1 and the input current is measuredas the second test signal TS2, two terminals of the N−1-th test unitDUTN−1a are connected.

Two terminals of the row switch SRa are connected, two terminals of theN-th column switch SNa are connected, and two terminals of each of othercolumn switches (S1 a, S2 a through SN−1a) are disconnected when thefirst row signal RS1 is activated, the row test enable signal RTS isdeactivated, and the N-th column output signal COSN is activated. If theinput current is applied as the first test signal TS1 and the inputcurrent is not measured as the second test signal TS2, two terminals ofthe N-th test unit DUTNa are disconnected. If the input current isapplied as the first test signal TS1 and the input current is measuredas the second test signal TS2, two terminals of the N-th test unit DUTNaare connected.

The first circuit 123 a includes the first through N-th column switchesS1 a, S2 a through SN−1a, SNa and the first through N-th test units DUT1a, DUT2 a through DUTN−1a, DUTNa. The first circuit 123 a will bedescribed with the reference to FIG. 3.

FIG. 3 is a circuit diagram illustrating an example embodiment of thefirst circuit included in the first row test block of FIG. 2.

Referring to FIG. 3, the first column switch S1 a includes a first passtransistor 141 a and a first inverter 124 a. The second column switch S2a includes a second pass transistor 142 a and a second inverter 125 a.The N−1-th column switch SN−1a includes a N−1-th pass transistor 143 aand a N−1-th inverter 126 a. The N-th column switch SNa includes a N-thpass transistor 144 a and a N-th inverter 127 a.

The first pass transistor 141 a includes a first transistor T1 and asecond transistor T2. The second pass transistor T2 includes a thirdtransistor T3 and a fourth transistor T4. The N−1-th pass transistor 143a includes a fifth transistor T5 and a sixth transistor T6. The N-thpass transistor 144 a includes a seventh transistor T7 and a eighthtransistor T8.

The first inverter 124 a generates an inverted first column outputsignal by inverting the first column output signal COS1. A drainterminal of the first transistor T1 is connected to a second node 121 a,a gate terminal of the first transistor T1 receives the first columnoutput signal COS1, and a source terminal of the first transistor T1 isconnected to a third node 128 a. A drain terminal of the secondtransistor T2 is connected to the second node 121 a, a gate terminal ofthe second transistor T2 receives the inverted first column outputsignal, and a source terminal of the second transistor T2 is connectedto the third node 128 a. A first terminal of the first test unit DUT1 ais connected to the third node 128 a, and a second terminal of the firsttest unit DUT1 a is connected to a first node 122 a.

The second inverter 125 a generates an inverted second column outputsignal by inverting the second column output signal COS2. A drainterminal of the third transistor T3 is connected to the second node 121a, a gate terminal of the third transistor T3 receives the second columnoutput signal COS2, and a source terminal of the third transistor T3 isconnected to a fourth node 129 a. A drain terminal of the fourthtransistor T4 is connected to the second node 121 a, a gate terminal ofthe fourth transistor T4 receives the inverted second column outputsignal, and a source terminal of the fourth transistor T4 is connectedto the fourth node 129 a. A first terminal of the second test unit DUT2a is connected to the fourth node 129 a, and a second terminal of thesecond test unit DUT2 a is connected to the first node 122 a.

The N−1-th inverter 126 a generates an inverted N−1-th column outputsignal by inverting the N−1-th column output signal COSN−1. A drainterminal of the fifth transistor T5 is connected to the second node 121a, a gate terminal of the fifth transistor T5 receives the N−1-th columnoutput signal COSN−1, and a source terminal of the fifth transistor T5is connected to a fifth node 130 a. A drain terminal of the sixthtransistor T6 is connected to the second node 121 a, a gate terminal ofthe sixth transistor T6 receives the inverted N−1-th column outputsignal, and a source terminal of the sixth transistor T6 is connected tothe fifth node 130 a. A first terminal of the N−1-th test unit DUTN−1ais connected to the fifth node 130 a, and a second terminal of theN−1-th test unit DUTN−1a is connected to the first node 122 a.

The N-th inverter 127 a generates an inverted N-th column output signalby inverting the N-th column output signal COSN. A drain terminal of theseventh transistor T7 is connected to the second node 121 a, a gateterminal of the seventh transistor T7 receives the N-th column outputsignal COSN, and a source terminal of the seventh transistor T7 isconnected to a sixth node 131 a. A drain terminal of the eighthtransistor T8 is connected to the second node 121 a, a gate terminal ofthe eighth transistor T8 receives the inverted N-th column outputsignal, and a source terminal of the eighth transistor T8 is connectedto the sixth node 131 a. A first terminal of the N-th test unit DUTNa isconnected to the sixth node 131 a, and a second terminal of the N-thtest unit DUTNa is connected to the first node 122 a.

FIGS. 4 through 7 are diagrams illustrating example embodiments oflayouts of the first, second, N−1-th, and N-th test units included inthe first row test block of FIG. 2. These layouts show the same layoutpattern, but have different design rules among the layout pattern.

FIG. 4 shows an example embodiment of layout of the first test unit DUT1a. A first metal 132 a is connected to the first node 122 a. A secondmetal 133 a is connected to the third node 128 a. Distance between thefirst metal 132 a and the second metal 133 a is 10 U (Units).

FIG. 5 shows an example embodiment of layout of the second test unitDUT2 a. A third metal 134 a is connected to the first node 122 a. Afourth metal 135 a is connected to the fourth node 129 a. Distancebetween the third metal 134 a and the fourth metal 135 a is 9 U.

FIG. 6 shows an example embodiment of layout of the N−1-th test unitDUTN−1a. A fifth metal 136 a is connected to the first node 122 a. Asixth metal 137 a is connected to the fifth node 130 a. Distance betweenthe fifth metal 136 a and the sixth metal 137 a is 5 U.

FIG. 7 shows an example embodiment of layout of the N-th test unitDUTNa. A seventh metal 138 a is connected to the first node 122 a. Aneighth metal 139 a is connected to the sixth node 131 a. Distancebetween the seventh metal 137 a and the eighth metal 139 a is 4 U.

Referring to FIGS. 2, and 4 through 7, in an example embodiment, thefact that all of the first through N-th test units DUT1 a, DUT2 athrough DUTN−1a, DUTNa are opened may be indicated by one test when thefirst row signal RS1 is activated, activated row test enable signal RTSis applied to the row test controller 160, the input current is appliedas the first test signal TS1, and the input current is not measured asthe second test signal TS2. In this case, the fact that minimum distancebetween metals in the design rule is equal to or smaller than 4 U may beindicated, and it is not required to separately perform short test ofeach of the first through N-th test units DUT1 a, DUT2 a throughDUTN−1a, DUTNa again.

In another example embodiment, the fact that not all of the firstthrough N-th test units DUT1 a, DUT2 a through DUTN−1a, DUTNa are openedmay be indicated when the first row signal RS1 is activated, activatedrow test enable signal RTS is applied to the row test controller 160,the input current is applied as the first test signal TS1, and the inputcurrent is measured as the second test signal TS2. In this case, thetest circuit 110 separately performs short test of each of the firstthrough N-th test units DUT1 a, DUT2 a through DUTN−1a, DUTNa again bydeactivating the row test enable signal RTS, activating the firstthrough N-th column output signals COS1, COS2 through COSN−1, COSNsequentially. After short tests are performed again, the fact that theminimum distance between metals in the design rules is 5 U may beindicated when two terminals of the N−1-th test unit DUTN−1a aredisconnected and two terminals of the N-th test unit DUTNa areconnected.

FIG. 8 is a block diagram illustrating the first row test block includedin the test system of FIG. 1.

Referring to FIG. 8, the first row test block 120 b may include a rowswitch SRb, and the first through 2N-th column switches S1 b, S2 bthrough SN−1b, SNb, SN+1b, SN+2b through S2N−1b, and S2Nb. The secondthrough M-th row test blocks RTC2, RTCM−1, RTCM included in the testsystem 100 of FIG. 1 may have the same or similar structure with thefirst row test block 120 b.

The first test signal TS1 may be applied to a first terminal of the rowswitch SRb. A second terminal of the row switch SRb may be connected toa first node 122 b. The first and second terminals of the row switch SRbmay be connected or disconnected based on the first row signal RS1. Thesecond test signal TS2 may be output from a second node 121 b. Firstterminals of the first through N-th column switches S1 b, S2 b throughSN−1b, SNb may be connected to the second node 122 b. Second terminalsof the first through N-th column switches S1 b, S2 b through SN−1b, SNbmay be connected to first terminals of the N+1-th through 2N-th columnswitches SN+1a, SN+2a through S2N−1a, S2Nb through the first throughN-th test units DUT1 b, DUT2 b through DUTN−1b, DUTNb respectively.Second terminals of the N+1-th through 2N-th column switches SN+1a,SN+2a through S2N−1a, S2Nb may be connected to the first node 122 b. Thefirst and second terminals of each of the first through N-th columnswitches S1 b, S2 b through SN−1b, SNb may be connected or disconnectedbased on each of the first through N-th column output signals COS1, COS2through COSN−1, COSN, and the first and second terminals of each of theN+1-th through 2N-th column switches SN+1a, SN+2a through S2N−1a, S2Nbmay be connected or disconnected based on each of the first through N-thcolumn output signals COS1, COS2 through COSN−1, COSN.

Operation of the first row test block 120 b may be understood based onthe reference to FIG. 2.

FIG. 9 is a block diagram illustrating a row test controller included inthe test system of FIG. 1.

Referring to FIG. 9, the row test controller 160 may include firstthrough N-th OR gates 181, 182, 183 through 184. The first OR gate 181may generate the first column output signal COS1 by performing logic ORoperation on the row test enable signal RTS and the first column signalCS1. The second OR gate 182 may generate the second column output signalCOS2 by performing logic OR operation on the row test enable signal RTSand the second column signal CS2. The N−1-th OR gate 183 may generatethe N−1-th column output signal COSN−1 by performing logic OR operationon the row test enable signal RTS and the N−1-th column signal CSN−1.The N-th OR gate 184 may generate the N−1-th column output signal COSNby performing logic OR operation on the row test enable signal RTS andthe N-th column signal CSN.

FIG. 10 is a sectional view of a test system according to an exampleembodiment.

Referring to FIG. 10, the test system 100 of FIG. 1 may be implementedon a silicon substrate 220. The test system 100 may include a pluralityof row input signal metals 151, 152, first and second test signal metals111, 112, row test enable signal metal 161, and a plurality of columninput signal metals 171, 172 on a surface of the silicon substrate 220.

An insulation layer 210 may be formed to be stacked on the siliconsubstrate 220. The insulation layer 210 may include a plurality of rowinput signal pads PR1, PRP, first and second test signal pads PTS1,PTS2, a row test enable signal pad PRTS, and a plurality of column inputsignal pads PC1, PCQ on a surface of the insulation layer 220. Theinsulation layer 220 may include first connection metals 211, 212connecting the row input signal pads PR1, PRP and the row input signalmetals 151, 152 respectively. The insulation layer 220 may include asecond connection metal 213 connecting the first test signal pad PTS1and the first test signal metal 111. The insulation layer 220 mayinclude a third connection metal 214 connecting the second test signalpad PTS2 and the second test signal metal 112. The insulation layer 220may include a fourth connection metal 215 connecting the row test enablesignal pad PRTS and the row test enable signal metal 161. The insulationlayer 220 may include fifth connection metals 216, 217 connecting thecolumn input signal pads PC1, PCQ and the column input signal metals171, 172.

The row input signals RIS1, RISP may be provided to the row decoder 150through the row input signal pads PR1, PRP, the first connection metals211, 212, and the row input signal metals 151, 152, respectively. Thecolumn input signals CIS1, CISQ may be provided to the column decoder170 through the column input signal pads PC1, PCQ, the fifth connectionmetals 216, 217, and the column input signal metals 171, 172,respectively. The row test enable signal RTS may be provided to the rowtest controller 160 through the row test enable signal pad PRTS, thefourth connection metal 215, and the row test enable signal metal 161.The first test signal TS1 generated by an external current source 231may be provided to the test circuit 110 through the first test signalpad PTS1, the second connection metal 213, and the first test signalmetal 111. The second test signal TS2 generated by the test circuit 110may be provided to an external current measurement circuit 232 throughthe second test signal metal 112, the third connection metal 214, andthe second test signal pad PTS2.

FIG. 11 is a block diagram illustrating a test system according toanother example embodiment.

Referring to FIG. 11, a test system 300 includes a row decoder 350, acolumn decoder 360, and a test circuit 310. The row decoder 350activates one of first through M-th row signals RS1, RS2 through RSM−1,RSM based on a plurality of row input signals RIS1 through RISP. M is apositive integer. The column decoder 360 activates one of signals, whichincludes a row test enable signal RTS and first through N-th columnsignals CS1 through CSN−1, CSN, based on a plurality of column inputsignals CIS1 through CISQ. N is a positive integer. The test circuit 310includes first through M-th row test blocks RTC1(320), RTC2 throughRTCM−1, RTCM, each of which includes first through N-th test units DUT1through DUTN−1, DUTN. The first through M-th row test blocks RTC1, RTC2through RTCM−1, RTCM correspond to the first through M-th row signalsRS1, RS2 through RSM−1, RSM, respectively. The test circuit 310simultaneously performs open test of the first through N-th test unitsincluded in a row test block, which corresponds to activated row signalamong the first through M-th row signals RS1, RS2 through RSM−1, RSM,based on first and second test signals TS1, TS2 and the first throughN-th column signals CS1 through CSN−1, CSN when the row test enablesignal RTS is activated.

The test circuit 310 may perform open test of a test unit, whichcorresponds to the activated row signal among the first through M-th rowsignals RS1, RS2 through RSM−1, RSM and activated column signal amongthe first through N-th column signals CS1 through CSN−1, CSN, based onthe first and second test signals TS1, TS2 when the row test enablesignal RTS is deactivated.

A procedure of simultaneous open test of the first through N-th testunits DUT1, DUT2 through DUTN−1, DUTN and a procedure of separate opentest of the first through N-th test units DUT1, DUT2 through DUTN−1,DUTN will be described with the reference to FIG. 12.

FIG. 12 is a block diagram illustrating the first row test blockincluded in the test system of FIG. 11.

Referring to FIG. 12, the first row test block 320 may include firstthrough third row switches SR1, SR2, and SR3, and first through 2N-thcolumn switches S1 through SN−1, SN, SN+1 through S2N−1, S2N. The secondthrough M-th row test blocks RTC2, RTCM−1, RTCM included in the testsystem 300 of FIG. 11 may have the same or similar structure with thefirst row test block 320.

The first test signal TS1 may be applied to a first terminal of thefirst row switch SR1. A second terminal of the first row switch SR1 maybe connected to a first node 322. The first and second terminals of thefirst row switch SR1 may be connected or disconnected based on the firstrow signal RS1. A first terminal of the L+1-th test unit may beconnected to a second terminal of the L-th test unit. L is a positiveinteger less than N. In other words, the second terminal of the firsttest unit DUT1 may be connected to the first terminal of the second testunit through a fourth node 324, and the second terminal of the N−1-thtest unit DUTN−1 may be connected to the first terminal of the N-th testunit DUTN through a sixth node 326. A first terminal of the second rowswitch SR2 may be connected to the first node 322. A second terminal ofthe second row switch SR2 may be connected to a first terminal of thefirst test unit DUT1 through a third node 323. The first and secondterminals of the second row switch SR2 may be connected or disconnectedbased on the row test enable signal RTS. A first terminal of the thirdrow switch SR3 may be connected to a second terminal of the N-th testunit DUTN through a seventh node 327. A second terminal of the third rowswitch SR3 may be connected to a second node 321. The second test signalTS2 may be output from the second node 321. The first and secondterminals of the third row switch SR3 may be connected or disconnectedbased on the row test enable signal RTS. First terminals of the firstthrough N-th column switches S1 through SN−1, SN may be connected to thesecond node 321. Second terminals of the first through N-th columnswitches S1 through SN−1, SN may be connected to the second terminals ofthe first through N-th test units DUT1 through DUTN−1, DUTNrespectively. The first and second terminals of each of the firstthrough N-th column switches S1 through SN−1, SN may be connected ordisconnected based on each of the first through N-th column signal CS1through CSN−1, CSN. First terminals of the N+1-th through 2N-th columnswitches SN+1 through S2N−1, S2N may be connected to the first node 322.Second terminals of the N+1-th through 2N-th column switches SN+1through S2N−1, S2N are connected to the first terminals of the firstthrough N-th test units DUT1 through DUTN−1, DUTN respectively. Thefirst and second terminals of each of the N+1-th through 2N-th columnswitches SN+1 through S2N−1, S2N are connected or disconnected based oneach of the first through N-th column signal CS1 through CSN−1, CSN.

The first and second terminals of the first row switch SR1 may beconnected (shorted) when the first row signal RS1 is activated. Thefirst and second terminals of the first row switches SR1 may bedisconnected (opened) when the first row signal RS1 is deactivated. Thefirst and second terminals of the second row switch SR2 may be connectedwhen the row test enable signal RTS is activated. The first and secondterminals of the second row switches SR2 may be disconnected when therow test enable signal RTS is deactivated. The first and secondterminals of the third row switch SR3 may be connected when the row testenable signal RTS is activated. The first and second terminals of thethird row switches SR3 may be disconnected when the row test enablesignal RTS is deactivated. The first and second terminals of each of thefirst through 2N-th column switches S1 through SN−1, SN, SN+1 throughS2N−1, S2N are connected when each of the first through N-th columnsignal CS1 through CSN−1, CSN is activated. The first and secondterminals of each of the first through 2N-th column switches S1 throughSN−1, SN, SN+1 through S2N−1, S2N are disconnected when each of thefirst through N-th column signal CS1 through CSN−1, CSN is deactivated.

In an example embodiment, the first through N-th test units DUT1, DUTN−1through DUTN may have the same circuit structure, but may have differentlayout patterns. Example embodiments of layouts of the first throughN-th test units DUT1, DUTN−1 through DUTN will be described with thereferences to FIGS. 13 through 15

Two terminals of the first row switch SR1 are connected, two terminalsof the second row switches SR2 are connected, and two terminals of thethird row switches SR3 are connected when the first row signal RS1 isactivated and the row test enable signal RTS is activated. Because therow test enable signal RTS is activated, the first through N-th columnsignals CS1 through CSN−1, CSN are deactivated and two terminals of eachof the first through 2N-th column switches S1 through SN−1, SN, SN+1through S2N−1, S2N are disconnected. If the input current is applied asthe first test signal TS1 and the input current is measured as thesecond test signal TS2, two terminals of every first through N-th testunits DUT1 through DUTN−1, DUTN are connected and the result of the opentest of the first through N-th test units DUT1 through DUTN−1, DUTNrepresents success. In other words, the fact that all of the firstthrough N-th test units DUT1 through DUTN−1, DUTN are shorted may beindicated by one test.

If the input current is applied as the first test signal TS1 and theinput current is not measured as the second test signal TS2, twoterminals of at least one of the first through N-th test units DUT1through DUTN−1, DUTN is disconnected and the result of the open test ofthe first through N-th test units DUT1 through DUTN−1, DUTN representsfailure. In other words, the fact that not all of the first through N-thtest units DUT1 through DUTN−1, DUTN are shorted may be indicated. Inthis case, the test circuit 310 separately performs open test of each ofthe first through N-th test units DUT1, DUTN−1 through DUTN again bydeactivating the row test enable signal RTS, activating the firstthrough N-th column signals CS1 through CSN−1, CSN sequentially.

Two terminals of the first row switch SR1 are connected, two terminalsof the first column switch S1 are connected, and two terminals of theN+1-th column switch SN+1 are connected, two terminals of the second rowswitch SR2 are disconnected, two terminals of the third row switch SR3are disconnected, and two terminals of each of other column switchesSN−1, SN, S2N−1, and S2N are disconnected when the first row signal RS1is activated, the row test enable signal RTS is deactivated, the firstcolumn signal CS1 is activated, and other column signals CSN−1, CSN aredeactivated. If the input current is applied as the first test signalTS1 and the input current is measured as the second test signal TS2, twoterminals of the first test unit DUT1 a are connected. If the inputcurrent is applied as the first test signal TS1 and the input current isnot measured as the second test signal TS2, two terminals of the firsttest unit DUT1 a are disconnected.

Two terminals of the first row switch SR1 are connected, two terminalsof the N−1-th column switch SN−1 are connected, and two terminals of the2N−1-th column switch S2N−1 are connected, two terminals of the secondrow switch SR2 are disconnected, two terminals of the third row switchSR3 are disconnected, and two terminals of each of other column switchesS1, SN, SN+1, and S2N are disconnected when the first row signal RS1 isactivated, the row test enable signal RTS is deactivated, the N−1-thcolumn signal CSN−1 is activated, and other column signals CS1, CSN aredeactivated. If the input current is applied as the first test signalTS1 and the input current is measured as the second test signal TS2, twoterminals of the N−1-th test unit DUTN−1 are connected. If the inputcurrent is applied as the first test signal TS1 and the input current isnot measured as the second test signal TS2, two terminals of the N−1-thtest unit DUTN−1 are disconnected.

Two terminals of the first row switch SR1 are connected, two terminalsof the N-th column switch SN are connected, and two terminals of the2N-th column switch S2N are connected, two terminals of the second rowswitch SR2 are disconnected, two terminals of the third row switch SR3are disconnected, and two terminals of each of other column switches S1,SN−1, SN+1, and S2N−1 are disconnected when the first row signal RS1 isactivated, the row test enable signal RTS is deactivated, the N-thcolumn signal CSN is activated, and other column signals CS1, CSN−1 aredeactivated. If the input current is applied as the first test signalTS1 and the input current is measured as the second test signal TS2, twoterminals of the N-th test unit DUTN are connected. If the input currentis applied as the first test signal TS1 and the input current is notmeasured as the second test signal TS2, two terminals of the N-th testunit DUTN are disconnected.

FIGS. 13 through 15 are diagrams illustrating example embodiments oflayouts of the first, N−1-th, and N-th test units included in the firstrow test block of FIG. 12. These layouts show the same layout pattern,but have different design rules among the layout pattern.

FIG. 13 shows an example embodiment of layout of the first test unitDUT1. A first metal 331, which is the first terminal of the first testunit DUT1, is connected to the third node 323. A third metal 335, whichis the second terminal of the first test unit DUT1, is connected to thefourth node 324. A second metal 333 is connected to the first metal 331through a first contact 332. The second metal 333 is connected to thethird metal 335 through a second contact 334. Each of the first contact332 and the second contact 334 has a size of 4 U*4 U.

FIG. 14 shows an example embodiment of layout of the N−1-th test unitDUTN−1. A fourth metal 336, which is the first terminal of the N−1-thtest unit DUTN−1, is connected to the fifth node 325. A sixth metal 340,which is the second terminal of the N−1-th test unit DUTN−1, isconnected to the sixth node 326. A fifth metal 338 is connected to thefourth metal 336 through a third contact 337. The fifth metal 338 isconnected to the sixth metal 340 through a fourth contact 339. Each ofthe third contact 337 and the fourth contact 339 has a size of 3 U*3 U.

FIG. 15 shows an example embodiment of layout of the N-th test unitDUTN. A seventh metal 341, which is the first terminal of the N-th testunit DUTN, is connected to the sixth node 326. A ninth metal 345, whichis the second terminal of the N-th test unit DUTN, is connected to theseventh node 327. An eighth metal 343 is connected to the seventh metal341 through a fifth contact 342. The eighth metal 343 is connected tothe ninth metal 345 through a sixth contact 344. Each of the fifthcontact 342 and the sixth contact 344 has a size of 2 U*2 U.

Referring to FIGS. 12 through 15, in an example embodiment, the factthat all of the first through N-th test units DUT1 through DUTN−1, DUTNare shorted may be indicated by one test when the first row signal RS1is activated, the row test enable signal RTS is activated, the inputcurrent is applied as the first test signal TS1, and the input currentis measured as the second test signal TS2. In this case, the fact thatminimum size of contact in the design rule is equal to or smaller than 2U*2 U may be indicated, and it is not required to separately performopen test of each of the first through N-th test units DUT1 throughDUTN−1, DUTN again.

In another example embodiment, the fact that not all of the firstthrough N-th test units DUT1 through DUTN−1, DUTN are shorted may beindicated when the first row signal RS1 is activated, the row testenable signal RTS is activated, the input current is applied as thefirst test signal TS1, and the input current is not measured as thesecond test signal TS2. In this case, the test circuit 310 separatelyperforms open test of each of the first through N-th test units DUT1through DUTN−1, DUTN again by deactivating the row test enable signalRTS, activating the first through N-th column signals CS1 through CSN−1,CSN sequentially. After open tests are performed again, the fact thatthe minimum size of contact in the design rules is 3 U*3 U may beindicated when two terminals of the N−1-th test unit DUTN−1 areconnected and two terminals of the N-th test unit DUTN are disconnected.

FIG. 16 is a sectional view of an example embodiment implementing thetest system of FIG. 11.

Referring to FIG. 16, the test system 300 of FIG. 11 may be implementedon a silicon substrate 420. The test system 300 may include a pluralityof row input signal metals 351, 352, first and second test signal metals311, 312, and a plurality of column input signal metals 361, 362 on asurface of the silicon substrate 420.

An insulation layer 410 may be formed to be stacked on the siliconsubstrate 420. The insulation layer 410 may include a plurality of rowinput signal pads PR1, PRP, first and second test signal pads PTS1,PTS2, and a plurality of column input signal pads PC1, PCQ on a surfaceof the insulation layer 410. The insulation layer 410 may include firstconnection metals 411, 412 connecting the row input signal pads PR1, PRPand the row input signal metals 351, 352 respectively. The insulationlayer 410 may include a second connection metal 413 connecting the firsttest signal pad PTS1 and the first test signal metal 311. The insulationlayer 410 may include a third connection metal 414 connecting the secondtest signal pad PTS2 and the second test signal metal 312. Theinsulation layer 410 may include fourth connection metals 415, 416connecting the column input signal pads PC1, PCQ and the column inputsignal metals 361, 362.

The row input signals RIS1, RISP may be provided to the row decoder 350through the row input signal pads PR1, PRP, the first connection metals411, 412, and the row input signal metals 351, 352, respectively. Thecolumn input signals CIS1, CISQ may be provided to the column decoder360 through the column input signal pads PC1, PCQ, the fourth connectionmetals 415, 416, and the column input signal metals 361, 362,respectively. The first test signal TS1 generated by an external currentsource 431 may be provided to the test circuit 310 through the firsttest signal pad PTS1, the second connection metal 413, and the firsttest signal metal 311. The second test signal TS2 generated by the testcircuit 310 may be provided to an external current measurement circuit432 through the second test signal metal 312, the third connection metal414, and the second test signal pad PTS2.

The foregoing is illustrative of example embodiments and is not to beconstrued as limiting thereof. Although a few example embodiments havebeen described, those skilled in the art will readily appreciate thatmany modifications are possible in the example embodiments withoutmaterially departing from the novel teachings and advantages of thepresent inventive concepts. Accordingly, all such modifications areintended to be included within the scope of the present inventiveconcepts as defined in the claims. Therefore, it is to be understoodthat the foregoing is illustrative of various example embodiments and isnot to be construed as limited to the specific example embodimentsdisclosed, and that modifications to the disclosed example embodiments,as well as other example embodiments, are intended to be included withinthe scope of the appended claims.

What is claimed is:
 1. A test system comprising: a row decoderconfigured to activate one of first through M-th row signals, where M isa positive integer, based on a plurality of row input signals; a columndecoder configured to activate one of first through N-th column signals,where N is a positive integer, based on a plurality of column inputsignals; a row test controller configured to output first through N-thcolumn output signals, which are activated, when a row test enablesignal is activated and output the first through N-th column signals asthe first through N-th column output signals respectively when the rowtest enable signal is deactivated; and a test circuit including firstthrough M-th row test blocks, each of which includes first through N-thtest units, wherein the first through M-th row test blocks correspond tothe first through M-th row signals, respectively, and wherein the testcircuit simultaneously performs a short test of the first through N-thtest units included in a row test block, which corresponds to activatedrow signal among the first through M-th row signals, based on first andsecond test signals and the first through N-th column output signalswhen the row test enable signal is activated.
 2. The test system ofclaim 1, wherein the test circuit performs the short test of a testunit, which corresponds to the activated row signal among the firstthrough M-th row signals and activated column output signal among thefirst through N-th column output signals, based on the first and secondtest signals when the row test enable signal is deactivated.
 3. The testsystem of claim 1, wherein a result of the short test of the firstthrough N-th test units represents success when an input current isapplied as the first test signal and the input current is not measuredas the second test signal, wherein the result of the short test of thefirst through N-th test units represents failure when the input currentis applied as the first test signal and the input current is measured asthe second test signal.
 4. The test system of claim 3, wherein if theresult of the short test of the first through N-th test units representsfailure, the row test enable signal is deactivated and the test circuitseparately performs the short test of each of the first through N-thtest units included in the row test block, which corresponds to theactivated row signal among the first through M-th row signals, again. 5.The test system of claim 1, wherein the K-th row test block, where K isa positive integer equal to or less than M, includes a row switch andfirst through N-th column switches, wherein the first test signal isapplied to a first terminal of the row switch, a second terminal of therow switch is connected to a first node, and the first and secondterminals of the row switch are connected or disconnected based on theK-th row signal, and wherein the second test signal is output from asecond node, first terminals of the first through N-th column switchesare connected to the second node, second terminals of the first throughN-th column switches are connected to the first node through the firstthrough N-th test units respectively, and the first and second terminalsof each of the first through N-th column switches are connected ordisconnected based on each of the first through N-th column outputsignals.
 6. The test system of claim 1, wherein the K-th row test block,where K is a positive integer equal to or less than M, includes a rowswitch and first through 2N-th column switches, wherein the first testsignal is applied to a first terminal of the row switch, a secondterminal of the row switch is connected to a first node, and the firstand second terminals of the row switch are connected or disconnectedbased on the K-th row signal, and wherein the second test signal isoutput from a second node, first terminals of the first through N-thcolumn switches are connected to the second node, second terminals ofthe first through N-th column switches are connected to first terminalsof the N+1-th through 2N-th column switches through the first throughN-th test units respectively, second terminals of the N+1-th through2N-th column switches are connected to the first node, the first andsecond terminals of each of the first through N-th column switches areconnected or disconnected based on each of the first through N-th columnoutput signals, and the first and second terminals of each of the N+1-ththrough 2N-th column switches are connected or disconnected based oneach of the first through N-th column output signals.
 7. The test systemof claim 1, wherein the test system is embodied on a silicon substrate,and wherein the test system includes a plurality of row input signalmetals, first and second test signal metals, row test enable signalmetal, and a plurality of column input signal metals on the siliconsubstrate.
 8. The test system of claim 7 further comprising aninsulation layer on the silicon substrate, wherein the insulation layerincludes a plurality of row input signal pads, first and second testsignal pads, a row test enable signal pad, and a plurality of columninput signal pads on the insulation layer, wherein the insulation layerincludes first connection metals connecting the row input signal padsand the row input signal metals respectively, a second connection metalconnecting the first test signal pad and the first test signal metal, athird connection metal connecting the second test signal pad and thesecond test signal metal, a fourth connection metal connecting the rowtest enable signal pad and the row test enable signal metal, and fifthconnection metals connecting the column input signal pads and the columninput signal metals, wherein the row input signals are provided to therow decoder through the row input signal pads, the first connectionmetals, and the row input signal metals, respectively, wherein thecolumn input signals are provided to the column decoder through thecolumn input signal pads, the fifth connection metals, and the columninput signal metals, respectively, wherein the row test enable signal isprovided to the row test controller through the row test enable signalpad, the fourth connection metal, and the row test enable signal metal,wherein the first test signal generated by an external current source isprovided to the test circuit through the first test signal pad, thesecond connection metal, and the first test signal metal, and whereinthe second test signal generated by the test circuit is provided to anexternal current measurement circuit through the second test signalmetal, the third connection metal, and the second test signal pad.
 9. Atest system comprising: a row decoder configured to activate one offirst through M-th row signals, where M is a positive integer, based ona plurality of row input signals; a column decoder configured toactivate one of first through N-th column signals, where N is a positiveinteger, based on a plurality of column input signals; a test circuitincluding first through M-th row test blocks, each of which includesfirst through N-th test units; wherein the first through M-th row testblocks correspond to the first through M-th row signals, respectively,and wherein the test circuit simultaneously performs a test of the firstthrough N-th test units included in a row test block, which correspondsto activated row signal among the first through M-th row signals, basedon first and second test signals and the first through N-th columnoutput signals when the row test enable signal is activated.
 10. Thetest system of claim 9 wherein the test is a short test that representsfailure when a current is applied to a first node of the test unit andthe current is measured at a second node of the test unit.
 11. The testsystem of claim 9 wherein the test is an open test that representsfailure when a current is applied to a first node of the test unit andthe current is not measured at a second node of the test unit.
 12. Thetest system of claim 9 wherein the test circuit is embodied on a singlesilicon substrate.
 13. The test system of claim 12 wherein the pluralityof test circuit comprises a plurality of layout patterns in the singlesilicon substrate, at least two of which include different design rules.